On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

Linux平台下增强型定时器服务的研究

智能化的嵌入式产品普遍需要一定的实时性，这对定时机制提出了更高的要求。本文针对 linux 平台的用户态定时 器服务的现状，提出了增强型定时器的设计方案，主要是在多模式、并行性及时间粒度方面做了改时。     

激光旋转扫描测量系统中转轴标定及多视拼合

由于激光扫描一次只能测量给定视角可见的物体表面，若测量物体全方位的形状，必须通过旋转，从多个视角测量物体，并将多视数据拼合于同一坐标系。精确标定转台的中心轴线是旋转测量和多视拼合的关键。提出了一种标定转台中心轴线的新方法．该方法将一个标定球固定于转台上，通过旋转，测量不同位置的标定球，计算不同位置的球心及其所在平面的法矢。再利用几何变换计算球心所在圆的圆心，从而精确标定出转轴的方位，实现了多视测量数据在线自动拼合，提高了数据拼合的精度。对于精度为50μm的测量机。在半径80mm的旋转范围内，拼合误差约为70μm。与以前的方法相比，设计的转轴标定方法简单、高效。在其他安装转台的测量系统中同样适用。     

多线程技术在航班规则检查中的应用

多线程程序设计技术在开发并行性和提高系统性能等方面的应用日益广泛.分析了线程和多线程程序设计的概念和基本思想,并结合在航班优化系统中航班规则检查的应用实例,说明了多线程程序设计的实现方法.     

有效消除多视拼接累计误差的大曲面测量方法

为了提高大尺寸曲面测量精度,综合利用精密机械、光电技术、CAD/CAM/CAT和自动控制等科学技术,将高精度测量设备与数控加工设备相结合,实现了大尺寸曲面在线检测加工一体化。在详细分析影响多视序列子轮廓拼接精度原因的基础上,为了减小多视拼接累计误差的影响,提出了基于互为基准的轮廓拼接策略和基于整体误差补偿的拼接方法,按照轮廓的封闭连续拼接误差最终为零的原则,实现累计误差的二次分配,减少序列轮廓数据连续拼接累计误差。实验结果表明:系统测量精度优于20 μm。     

A SAT Solver Using Reconfigurable Hardware and Virtual Logic

In this paper, we present the architecture of a new SAT solver using reconfigurable logic and a virtual logic scheme. Our main contributions include new forms of massive fine-grain parallelism, structured design techniques based on iterative logic arrays that reduce compilation times from hours to minutes, and a decomposition technique that creates independent subproblems that may be concurrently solved by unconnected FPGAs. The decomposition technique is the basis of the virtual logic scheme, since it allows solving problems that exceed the hardware capacity. Our architecture is easily scalable. Our results show several orders of magnitude speedup compared with a state-of-the-art software implementation, and also with respect to prior SAT solvers using reconfigurable hardware.     

异构计算环境中循环级并行性提取及调度

首先给出了循环最大加速比的定义,它是循环体中隐含并行性大小的度量。并且讨论了Ｄｏ循环的各种类型和它们的相关性以及隐含的并行性。在异构环境中,如何开发这些并行性,文中给出了几种方法,这就是异构计算消除串行瓶颈,异构Ｄｏ＿ａｌｌ＿ｌｏｏｐ调度,异构Ｄｏ＿ａ＿ｃｒｏｓｓ调度。无论在理论分析还是在实验结果上,这些方法所取得的计算性能都优于同构计算。     

一种支持多重循环软件流水的寄存器结构

寄存器结构及其分配是软件流水算法的关键之一.为支持多重循环的软件流水,该文提出一种新颖的寄存器结构：半共享跳跃式流水寄存器堆.它可以有效地解决多重循环软件流水下的特殊问题,即：同层次和跨层次的寄存器重命名问题以及断流问题;有效地消除外层循环的体间读写相关,提高程序的指令级并行度.它有3种分配方式可供灵活使用：单个寄存器、流水寄存器和寄存器组方式.流水寄存器方式对生存期确定的、局限于一个循环层次的寄存器重命名问题提供简单而有效的支持.寄存器组分配方式解决了多重循环软件流水时变量生存期不确定的情况.跳跃操作为     

具有最大并行度的合流性主动规则执行模型

合流性反映了主动规则集确定性行为特性。目前保证合流性的主动规则执行算法基本是串行的,而已有的并行规则执行算法并不保证合流性结果。本文扩展了已有的主动规则执行模型,给出具有最大并行度的合流性主动规则处理算法,并证明了该算的正确性。     

面向深度学习图像分类的GPU并行方法研究

针对深度学习图像分类场景中多GPU并行后传输效率低的问题,提出一种低时间复杂度的Ring All Reduce改进算法。通过分节点间隔配对原则优化数据传输流程,缓解传统参数服务器并行结构的带宽损耗。基于数据并行难以支撑大规模网络参数及加速延缓的问题,根据深度学习主干网络所包含的权重参数低于全连接层权重参数、同步开销小、全连接层权重大与梯度传输开销过高等特点,提出GPU混合并行优化算法,将主干网络进行数据并行,全连接层进行模型并行,并通过改进的Ring All Reduce算法实现各节点之间的并行后数据通信,用于基于深度学习模型的图像分类。在Cifar10和mini ImageNet两个公共数据集上的实验结果表明,该算法在保持分类精度不变的情况下可以获得更好的加速效果,相比数据并行方法,可达到近45%的提升效果。